1. Field
Example embodiments relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same in which poly grains are minimized in an active region of a peripheral/core area of a substrate.
2. Description of the Related Art
Generally, conventional manufacturing methods for semiconductor devices usually require device isolation layers for electrically separating unit conductive structures, such as gate structures, in the semiconductor device. One of the most widely known processes for forming a device isolation layer is a field oxidation process. According to the field oxidation formation process, an anti-oxidation pattern is formed on an active region of a substrate on which the unit conductive structures for the semiconductor device and an oxide layer is formed on a field region surrounding and defining the active region in a furnace. The above field oxidation process has been primarily based on a thermal diffusion process in a horizontal direction parallel with the substrate, and thus has had many limitations for forming the device isolation layer because the device isolation layer requires electrical insulation in a vertical direction perpendicular to the substrate. For that reason, a shallow-trench isolation (STI) process has been suggested, in which a shallow trench is formed around the active region to thereby define the active region and the shallow trench is filled with an insulation layer such as an oxide layer.
However, the conventional STI process requires many processing steps for device isolation, and thus has high process complexity and low process efficiency due to the high process complexity. In addition, continued increased device integration and continued reduction of the design rule in semiconductor devices result in the deterioration of gap-fill characteristics of the insulation layer in the trench.
For addressing the above-mentioned drawbacks of the conventional STI process, there has been suggested a process in which the active region is actively formed on a substrate to thereby passively form the device isolation layer in a process that reverses the steps of the conventional STI process in which the device isolation layer is actively formed in the trench of the substrate to thereby passively define the active region of the substrate.
For example, in the active-formation process, an insulation layer is formed on a substrate and partially removed from the substrate to thereby form an opening through which the active region of the substrate is exposed, and then an epitaxial layer is grown from a surface of the substrate in the active region by a selective epitaxial growth (SEG) process. Accordingly, the insulation layer surrounding the epitaxial layer in the active region is passively formed in the device isolation layer in a field region of the substrate. However, under this approach, various SEG process failures have been generated at a boundary surface between the epitaxial layer in the active region and the insulation layer in the field region due to the presence of crystal defects in the SEG process. A laser-induced epitaxial growth (LEG) process has been suggested for overcoming the above SEG process failures.
FIGS. 1A to 1F are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device in which an active region is formed on a substrate by an LEG process.
Referring to FIG. 1A, a lower oxide layer 12a, a nitride layer 12b and an upper oxide layer 12c are sequentially stacked on a substrate 10 to thereby form an insulation layer 12 on the substrate 10. A photoresist pattern 14 is formed on the insulation layer 12 in such a manner that portions of the insulation layer corresponding to an active region of the substrate 10 is exposed through the photoresist pattern 14.
Referring to FIG. 1B, an etching process is performed against the insulation layer 12 using the photoresist pattern 14 as an etching mask, to thereby form an opening 15 through which a portion of the substrate corresponding to the active region is exposed.
Referring to FIG. 1C, the photoresist pattern 14 is removed from the insulation layer 12 and a polysilicon layer (not shown) is formed on the substrate 10 to a sufficient thickness to fill up the opening 15. Then, the polysilicon layer is partially removed from the insulation layer 12 by a chemical mechanical polishing (CMP) process until a top surface of the insulation layer 12 is exposed, and thus the polysilicon layer remains in the opening 15. Accordingly, a polysilicon pattern 16 is formed on the substrate 10 in accordance with the opening 15, and an upper surface of the insulation layer 12 is coplanar with an upper surface of the polysilicon pattern 16.
Referring to FIGS. 1D and 1E, a laser is irradiated onto the substrate including the polysilicon layer 16, to thereby transform the polysilicon layer into a single-crystalline silicon pattern 18. For example, when an excimer laser is irradiated onto the upper surface of the polysilicon layer 16, the polysilicon layer 16 is momentarily melted and recrystallized into single-crystalline silicon to thereby form the single-crystalline silicon layer 18 in the opening 15. The single-crystalline silicon recrystallized from the polysilicon layer 16 is grown to the single-crystalline silicon layer 18 by a selective epitaxial growth (SEG) process using the crystal structure of the substrate 10, which can be single-crystal in structure, exposed through the opening 15. The above SEG process is performed on a conductive body and is not performed on a non-conductive body, and thus the single-crystalline silicon is relatively less grown at a boundary surface between the polysilicon layer 16 and the oxide layer 12c that is an insulation layer, to thereby form a groove 18a. 
Referring to FIG. 1F, the upper oxide layer 12c and an upper portion of the single-crystalline silicon layer 18 is removed from the substrate by a planarization process, to thereby remove the groove 18a from the substrate.
For example, the upper oxide layer 12c and the upper portion of the single-crystalline silicon layer 18 adjacent to the upper oxide layer 12c are planarized by a CMP process until a top surface of the nitride layer 12b is exposed, and thus an upper surface of the planarized single-crystalline silicon layer 18 is coplanar with the top surface of nitride layer 12b. Accordingly, the groove 18a interposed between the single-crystalline silicon layer 18 and the insulation layer 12 is removed from the substrate 10 and the active region 19 is formed on the substrate 10 between the adjacent residual insulation layers including the lower oxide layer 12a and the nitride layer 12b. 
The residual insulation layer surrounds and defines the active region 19 on the substrate 10; thus, conductive structures on the adjacent active regions are electrically separated from each other by the residual insulation layer 12 around the active region 19. That is, the residual insulation layer functions as a device-isolation layer in a semiconductor device.
However, when the optical energy of the laser is irradiated onto a relatively large area of the polysilicon layer 16, the polysilicon layer 16 is partially melted in the same surface to thereby form poly grains on a local area of the surface of the polysilicon layer 16. Accordingly, the polysilicon layer 16 is locally transformed into a single-crystalline silicon layer in the opening 15, which can thereby lead to deterioration of the electrical characteristics of the active region 19.
Particularly, in the case of a semiconductor device, an active region of a cell area has a relatively small size and has uniform distribution on the substrate, while an active region of a peripheral/core area has a relatively large size and has non-uniform distribution on the substrate. Therefore, when both the cell area and peripheral/core area of the substrate undergo the same LEG process, the optical energy of a laser sufficient for fully melting the polysilicon layer in the cell area is not sufficient for fully melting the polysilicon layer in the peripheral/core area, and thus the polysilicon layer in the peripheral/core area of the substrate is insufficiently melted by the same LEG process. Accordingly, some of the polysilicon layer in the peripheral/core area of the substrate is formed into poly grains and some is formed into the single-crystalline silicon layer. That is, the polysilicon layer is not uniformly formed into the single-crystalline silicon layer over the entire peripheral/core area of the substrate due to the local poly grains, which thereby deteriorates the uniformity of the resulting single-crystalline silicon layer and the electrical characteristics of the active region.
FIGS. 2A to 2D are views illustrating processing steps for transforming a polysilicon layer into poly grains in the peripheral/core area of the substrate.
Referring to FIGS. 2A and 2B, the polysilicon pattern 16 is formed in the opening 15 at the peripheral/core area of the substrate 10 by a deposition process and a CMP process, and the laser is irradiated onto the polysilicon pattern 16. The laser has the same optical energy as the laser that is irradiated onto polysilicon pattern at the cell area of the substrate 10. The portion of the optical energy of the laser exceeding the allowable light absorption degree of polysilicon is emitted to surrounding regions as thermal energy, as shown in FIG. 2B. Since the heat transfer through the single-crystalline silicon substrate 10 is much greater than that through the insulation layer 12, latent heat of the polysilicon pattern 16 is much greater at a side portion of the opening 15 making contact with the insulation layer 12 than at a central portion of the opening 15. Therefore, as shown in FIG. 2C, the polysilicon pattern 16 has a first melting depth D1 at the central portion of the opening 15 in accordance with the light absorption degree of the polysilicon and has a second melting depth D2 at the side portion of the opening 15 in accordance with the light absorption degree and the latent heat of the polysilicon pattern 16.
Referring to FIG. 2D, first grains G1 are formed on a residual polysilicon pattern in the central portion of the opening 15 along the first depth D1 and second grains G2 are formed on the residual polysilicon pattern in the side portion of the opening 15 along the second depth D2. Since the second depth D2 is much greater than the first depth D1 in the opening 15, the first grains become small-sized and dense and the second grains G2 become large-sized and sparse.
Therefore, when both of the cell area and the peripheral/core area of the substrate undergoes the same LEG process to form active regions of a semiconductor device, no poly grains are found at the cell area while a plurality of poly grains can still be found at the peripheral/core area because the peripheral/core area is relatively larger than the cell area.